ATM (Asynchronous Transfer Mode) cell streams are a commonly used way to format and transport data in a digital telecommunication system, for example over an ADSL (Asymmetric Digital Subscriber Line) link. An ATM cell comprises a 5-byte cell header and 48 bytes of payload. The cell header contains address and control data, which is used in a network to direct the transfer of the ATM cell from its source to its destination. The payload contains the data to be communicated to the destination.
International standards for ADSL and other forms of DSL (such as ITU-T Recommendation G992.1 entitled “Asymmetrical digital subscriber line (ADSL) transceivers,” ITU-T Recommendation G992.2 entitled “Splitterless asymmetric digital subscriber line (ADSL) transceivers,” ITU-T Recommendation G992.3 entitled “Asymmetric digital subscriber line transceivers-2 (ADSL2),” and ITU-T Recommendation G992.4 entitled “Splitterless asymmetric digital subscriber line transceivers 2 (splitterless ADSL2)”) define a method of conveying ATM cell streams over the DSL link. The method requires, amongst other things, that as cells are processed in the transmitting modem, the payload data bytes in each transmitted cell are scrambled using a self-synchronizing scrambler with polynomial X43+1. An equivalent way of describing the scrambling process is that for the stream of successive bits making up the input to the scrambler, x(n) (n=0, 1, 2, . . . ), the output of the scrambler y(n) is defined recursively as:y(n)=x(n)+y(n−43)
where + means addition modulo 2 (which is equivalent to logical “exclusive-or”). In other words, for each input bit, the output bit is the exclusive-or of that input bit and the output bit from 43 bit-times earlier.
The scrambling process is continuous over all bits of all payload bytes of all transmitted cells in a given ATM cell stream; it does not stop at the end of one byte or cell and start independently at the beginning of the next. Rather, the previous output bits which are used in the scrambling of new input bits are derived in the same way for every bit processed, without regard to byte or cell boundaries.
According to ATM standards, only the payload bytes are scrambled in this way: the header bytes are not scrambled and play no part in the process. For purposes of the scrambling process, the payload bytes of one cell are considered consecutive with the payload bytes of the preceding cell, ignoring the header bytes at the start of the new cell.
This scrambling scheme is also employed in a number of other contexts where ATM streams are passed between processing units over intermediate links.
A further common requirement for transmission of ATM cell streams over a DSL link concerns the ordering of the data bits in each byte of the ATM cell data being sent and received over the DSL link. When cells are passed across the external data interface of a DSL modem, DSL standards require the bits in each byte of the cell to be reversed in order. This is because whereas external to the modem, the most significant bit of each byte is considered to come first and is processed first, internally in the modem, the least significant bit of each byte is processed first, but the actual order of processing of the bits must be preserved. This reversal applies to all bytes of each ATM cell.
In an ATM-based modem in a telecommunication system, ATM cells may pass through the device for transmission at a high rate (for example in a multi-line ADSL or VDSL modem in a central-office DSL access multiplexer). It is therefore necessary to scramble the payload data of ATM cells efficiently. In prior art hardware oriented DSL modems, the ATM cell streams flow through fixed-function hardware circuits that include the logic to scramble the payload data stream. However, such system designs are typically much less adaptable to varying application requirements. In such hardware implementations of the scrambling function the data flow is fixed in an arrangement dictated by the physical movement of data through the hardware, and cannot be adapted or modified to suit different modes of use. For example, in such systems, the ‘state’ (the history of earlier output bits) is held internally within the scrambling hardware, rather than being passed in as and when scrambling is required. This means that re-using a hardware implementation to scramble multiple distinct data streams at the same time is either impossible, or certainly more complex to implement, since some arrangement must be made to allow the individual states for the different streams to be swapped in and out.
Current prior art DSL modems often use software to perform at least some of the various functions in a modem. One disadvantage of scramblers in current DSL modems is the inefficiency of such scramblers as the line-density and data-rates required of modems increase. As line-density and data-rates increase, so does the pressure on prior art modems to perform efficiently the individual processing tasks, such as scrambling, which make up the overall modem function.
Another disadvantage with current prior art scramblers is the software complexity required to implement such scramblers. Using conventional bit-wise instructions such as bit-wise shift, bit-wise exclusive-or, etc. may take many tens or even hundreds of cycles to perform the ATM scrambling operation for a single ATM cell. One processor may need to handle several hundred thousand ATM cells per second. Thus, the scrambling process for each cell can represent a significant proportion of the total computational cost for current prior art DSL modems, especially in the case of a multi-line system where one processor handles the operations for multiple lines. With increasing workloads, it becomes necessary to improve the efficiency of scrambling ATM cell payload bytes over that of such prior art modems.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.